RISC-V /Debug /Instruction Count (32-bit icount)

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Interpret as Instruction Count (32-bit icount)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (breakpoint)action0 (u)u0 (s)s0 (pending)pending 0 (m)m0count0 (hit)hit 0 (vu)vu 0 (vs)vs 0 (dmode)dmode 0type

action=breakpoint

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata1} when {tdata1-type} is 3.

This trigger matches when:

  1. An instruction retires after having been fetched in a privilege mode where the trigger is enabled. This explicitly includes all RET instructions from various modes.
  2. A trap is taken from a privilege mode where the trigger is enabled. This explicitly includes traps taken due to interrupts.

If more than one of the above events occur during a single instruction execution, the trigger still only matches once for that instruction.

đź“Ś NOTE

For use in single step, icount must match for traps where the instruction will not be reexecuted after the handler, such as illegal instructions that are emulated by privileged software and the instruction being emulated never retires. Ideally, icount would not match for traps where the instruction will later be retried by the handler, such as page faults where privileged software modifies the page tables and returns to the faulting instruction which ultimately retires. Trying to distinguish the two cases leads to complex rules, so instead the rule is simply that all traps match. See also stepicount.

When {icount-count} is greater than 1 and the trigger matches, then {icount-count} is decremented by 1.

When {icount-count} is 1 and the trigger matches, then {icount-pending} becomes set. In addition {icount-count} will become 0 unless it is hard-wired to 1.

The only exception to the above is when the instruction the trigger matched on is a write to the icount trigger. In that case {icount-pending} might or might not become set if {icount-count} was 1. Afterwards {icount-count} contains the newly written value.

When {icount-count} is 0 it stays at 0 until explicitly written.

When {icount-pending} is set, the trigger fires just before any further instructions are executed in a mode where the trigger is enabled. As the trigger fires, {icount-pending} is cleared. In addition, if {icount-count} is hard-wired to 1 then {icount-m}, {icount-s}, {icount-u}, {icount-vs}, and {icount-vu} are all cleared.

If the trigger fires with {icount-action}=0 then zero is written to the tval CSR on the breakpoint trap.

đź“Ś NOTE

The intent of {icount-pending} is to cleanly handle the case where {icount-action} is 0, {icount-m} is 0, {icount-u} is 1, {icount-count} is 1, and the U-mode instruction being executed causes a trap into M-mode. In that case we want the entire M-mode handler to be executed, and the debug trap to be taken before the next U-mode instruction.

đź“Ś NOTE

This trigger type is intended to be used as a single step for software monitor programs or native debug. Systems that support multiple privilege modes that want to debug software running in lower privilege modes don’t need to support {icount-count} greater than 1.

If {csr-textra32} or {csr-textra64} are implemented for this trigger, it only matches when the conditions set there are satisfied.

Fields

action

The action to take when the trigger fires. The values are explained in tab:action.

0 (breakpoint):

1 (debug mode):

2 (trace on):

3 (trace off):

4 (trace notify):

8 (external0):

9 (external1):

u

When set, enable this trigger in U-mode. This bit is hard-wired to 0 if the hart does not support U-mode.

s

When set, enable this trigger in S/HS-mode. This bit is hard-wired to 0 if the hart does not support S-mode.

pending

This bit becomes set when {icount-count} is decremented from 1 to 0. It is cleared when the trigger fires, which will happen just before executing the next instruction in one of the enabled modes.

m

When set, enable this trigger in M-mode.

count

The trigger will generally fire after {icount-count} instructions in enabled modes have been executed. See above for the precise behavior.

hit

If this bit is implemented, the hardware sets it when this trigger fires. The trigger’s user can set or clear it at any time. It is used to determine which trigger(s) fires. If the bit is not implemented, it is always 0 and writing it has no effect.

vu

When set, enable this trigger in VU-mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

vs

When set, enable this trigger in VS-mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

dmode
type

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